#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_CHIP_IMX9_CORTEX_M

menu "i.MX9 Chip Selection"

choice
	prompt "i.MX9 Core Configuration"
	default ARCH_CHIP_IMX95_M7

config ARCH_CHIP_IMX95_M7
	bool "i.MX95 Cortex-M7 Processor"
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU
	select ARMV7M_HAVE_ICACHE
	select ARMV7M_HAVE_DCACHE
	select ARMV7M_HAVE_ITCM
	select ARMV7M_HAVE_DTCM
	select IMX9_HAVE_MU

endchoice # i.MX9 Chip Selection

endmenu # "i.MX9 Chip Selection"

config IMX9_HAVE_MU
	bool
	default n

config IMX9_SCMI
	bool "SCMI Interface"
	default y
	depends on IMX9_MU5

if IMX9_SCMI

config IMX9_CLK_OVER_SCMI
	bool "Configure CLK over SCMI"
	default y

config IMX9_IOMUX_OVER_SCMI
	bool "Configure IOMUX over SCMI"
	default n

endif

config IMX9_WFI_AWAKES_AT_SYSTICK
	bool "WFI awakes at systick interrupts"
	default y
	---help---
	Configure the GPC to wake up from systick interrupts at WFI
	instruction

menu "i.MX9 Peripheral Selection"

config IMX9_EDMA
	bool "eDMA"
	default n
	select ARCH_DMA

menu "FLEXCAN Peripherals"

config IMX9_FLEXCAN
	bool
	default n
	select NET_CAN_HAVE_TX_DEADLINE
	select NET_CAN_HAVE_CANFD

config IMX9_FLEXCAN1
	bool "FLEXCAN1"
	default n
	select IMX9_FLEXCAN

config IMX9_FLEXCAN2
	bool "FLEXCAN2"
	default n
	select IMX9_FLEXCAN

config IMX9_FLEXCAN3
	bool "FLEXCAN3"
	default n
	select IMX9_FLEXCAN

config IMX9_FLEXCAN4
	bool "FLEXCAN4"
	default n
	select IMX9_FLEXCAN

config IMX9_FLEXCAN5
	bool "FLEXCAN5"
	default n
	select IMX9_FLEXCAN

if IMX9_FLEXCAN

config IMX9_FLEXCAN_TXMB
	int "Number of TX message buffers"
	default 5
	---help---
	This defines number of TX messages buffers. Please note that
	maximum number of all message buffers is 20

config IMX9_FLEXCAN_RXMB
	int "Number of RX message buffers"
	default 15
	---help---
	This defines number of RX messages buffers. Please note that
	maximum number of all message buffers is 20

endif

endmenu # FLEXCAN Peripherals

menu "FLEXCAN1 Configuration"
	depends on IMX9_FLEXCAN1

config FLEXCAN1_BITRATE
	int "CAN bitrate"
	depends on !(NET_CAN_CANFD)
	default 1000000

config FLEXCAN1_SAMPLEP
	int "CAN sample point"
	depends on !(NET_CAN_CANFD)
	default 80

config FLEXCAN1_ARBI_BITRATE
	int "CAN FD Arbitration phase bitrate"
	depends on NET_CAN_CANFD
	default 1000000

config FLEXCAN1_ARBI_SAMPLEP
	int "CAN FD Arbitration phase sample point"
	depends on NET_CAN_CANFD
	default 80

config FLEXCAN1_DATA_BITRATE
	int "CAN FD Data phase bitrate"
	depends on NET_CAN_CANFD
	default 4000000

config FLEXCAN1_DATA_SAMPLEP
	int "CAN FD Data phase sample point"
	depends on NET_CAN_CANFD
	default 90

endmenu # IMX9_FLEXCAN1

menu "FLEXCAN2 Configuration"
	depends on IMX9_FLEXCAN2

config FLEXCAN2_BITRATE
	int "CAN bitrate"
	depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD)
	default 1000000

config FLEXCAN2_SAMPLEP
	int "CAN sample point"
	depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD)
	default 80

config FLEXCAN2_ARBI_BITRATE
	int "CAN FD Arbitration phase bitrate"
	depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
	default 1000000

config FLEXCAN2_ARBI_SAMPLEP
	int "CAN FD Arbitration phase sample point"
	depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
	default 80

config FLEXCAN2_DATA_BITRATE
	int "CAN FD Data phase bitrate"
	depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
	default 4000000

config FLEXCAN2_DATA_SAMPLEP
	int "CAN FD Data phase sample point"
	depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD
	default 90

endmenu # IMX9_FLEXCAN2

menu "FLEXCAN3 Configuration"
	depends on IMX9_FLEXCAN3

config FLEXCAN3_BITRATE
	int "CAN bitrate"
	depends on !NET_CAN_CANFD
	default 1000000

config FLEXCAN3_SAMPLEP
	int "CAN sample point"
	depends on !NET_CAN_CANFD
	default 80

config FLEXCAN3_ARBI_BITRATE
	int "CAN FD Arbitration phase bitrate"
	depends on NET_CAN_CANFD
	default 1000000

config FLEXCAN3_ARBI_SAMPLEP
	int "CAN FD Arbitration phase sample point"
	depends on NET_CAN_CANFD
	default 80

config FLEXCAN3_DATA_BITRATE
	int "CAN FD Data phase bitrate"
	depends on NET_CAN_CANFD
	default 4000000

config FLEXCAN3_DATA_SAMPLEP
	int "CAN FD Data phase sample point"
	depends on NET_CAN_CANFD
	default 90

endmenu # IMX9_FLEXCAN3

menu "FLEXCAN4 Configuration"
	depends on IMX9_FLEXCAN4

config FLEXCAN4_BITRATE
	int "CAN bitrate"
	depends on !(NET_CAN_CANFD)
	default 4000000

config FLEXCAN4_SAMPLEP
	int "CAN sample point"
	depends on !(NET_CAN_CANFD)
	default 80

config FLEXCAN4_ARBI_BITRATE
	int "CAN FD Arbitration phase bitrate"
	depends on NET_CAN_CANFD
	default 4000000

config FLEXCAN4_ARBI_SAMPLEP
	int "CAN FD Arbitration phase sample point"
	depends on NET_CAN_CANFD
	default 80

config FLEXCAN4_DATA_BITRATE
	int "CAN FD Data phase bitrate"
	depends on NET_CAN_CANFD
	default 4000000

config FLEXCAN4_DATA_SAMPLEP
	int "CAN FD Data phase sample point"
	depends on NET_CAN_CANFD
	default 90

endmenu # IMX9_FLEXCAN4

menu "FLEXCAN5 Configuration"
	depends on IMX9_FLEXCAN5

config FLEXCAN5_BITRATE
	int "CAN bitrate"
	depends on !(NET_CAN_CANFD)
	default 5000000

config FLEXCAN5_SAMPLEP
	int "CAN sample point"
	depends on !(NET_CAN_CANFD)
	default 80

config FLEXCAN5_ARBI_BITRATE
	int "CAN FD Arbitration phase bitrate"
	depends on NET_CAN_CANFD
	default 5000000

config FLEXCAN5_ARBI_SAMPLEP
	int "CAN FD Arbitration phase sample point"
	depends on NET_CAN_CANFD
	default 80

config FLEXCAN5_DATA_BITRATE
	int "CAN FD Data phase bitrate"
	depends on NET_CAN_CANFD
	default 4000000

config FLEXCAN5_DATA_SAMPLEP
	int "CAN FD Data phase sample point"
	depends on NET_CAN_CANFD
	default 90

endmenu # IMX9_FLEXCAN5

menu "LPUART"

config IMX9_LPUART
	bool
	default n
	select ARCH_HAVE_SERIAL_TERMIOS

config IMX9_LPUART1
	bool "LPUART1"
	default n
	select IMX9_LPUART
	select LPUART1_SERIALDRIVER

config IMX9_LPUART2
	bool "LPUART2"
	default n
	select IMX9_LPUART
	select LPUART2_SERIALDRIVER

config IMX9_LPUART3
	bool "LPUART3"
	default n
	select IMX9_LPUART
	select LPUART3_SERIALDRIVER

config IMX9_LPUART4
	bool "LPUART4"
	default n
	select IMX9_LPUART
	select LPUART4_SERIALDRIVER

config IMX9_LPUART5
	bool "LPUART5"
	default n
	select IMX9_LPUART
	select LPUART5_SERIALDRIVER

config IMX9_LPUART6
	bool "LPUART6"
	default n
	select IMX9_LPUART
	select LPUART6_SERIALDRIVER

config IMX9_LPUART7
	bool "LPUART7"
	default n
	select IMX9_LPUART
	select LPUART7_SERIALDRIVER

config IMX9_LPUART8
	bool "LPUART8"
	default n
	select IMX9_LPUART
	select LPUART8_SERIALDRIVER

menu "LPUART Configuration"
	depends on IMX9_LPUART

config IMX9_LPUART_INVERT
	bool "Signal Invert Support"
	default n

config IMX9_LPUART_SINGLEWIRE
	bool "Signal Wire Support"
	default n

config IMX9_SERIAL_RXDMA_BUFFER_SIZE
	int "RX DMA buffer size"
	default 64
	depends on LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || LPUART4_RXDMA || \
	           LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || LPUART8_RXDMA
	---help---
		The DMA buffer size when using RX DMA to emulate a FIFO.

		When streaming data, the generic serial layer will be called
		every time the FIFO receives half this number of bytes.

		Value given here will be rounded up to next multiple of 64 bytes.

endmenu # LPUART Configuration

endmenu # LPUART

config IMX9_GPIO_IRQ
	bool "GPIO Interrupt Support"
	default n

menu "GPIO Interrupt Configuration"
	depends on IMX9_GPIO_IRQ

config IMX9_GPIO1_IRQ
	bool "GPIO1 Interrupt"
	default n

config IMX9_GPIO2_IRQ
	bool "GPIO2 Interrupt"
	default n

config IMX9_GPIO3_IRQ
	bool "GPIO3 Interrupt"
	default n

config IMX9_GPIO4_IRQ
	bool "GPIO4 Interrupt"
	default n

endmenu # GPIO Interrupt Configuration

config IMX9_LPI2C
	bool "LPI2C support"
	default n

config IMX9_LPSPI
	bool "LPSPI support"
	default n

menu "LPI2C Peripherals"

menuconfig IMX9_LPI2C1
	bool "LPI2C1"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C1

config IMX9_LPI2C1_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C1_DMA
	bool "Enable DMA for I2C1"
	default n
	depends on IMX9_LPI2C_DMA

config IMX9_LPI2C1_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C1_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C1

menuconfig IMX9_LPI2C2
	bool "LPI2C2"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C2

config IMX9_LPI2C2_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C2_DMA
	bool "Enable DMA for I2C2"
	default n
	depends on IMX9_LPI2C_DMA

config IMX9_LPI2C2_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C2_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C2

menuconfig IMX9_LPI2C3
	bool "LPI2C3"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C3

config IMX9_LPI2C3_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C3_DMA
	bool "Enable DMA for I2C3"
	default n
	depends on IMX9_LPI2C_DMA

config IMX9_LPI2C3_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C3_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C3

menuconfig IMX9_LPI2C4
	bool "LPI2C4"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C4

config IMX9_LPI2C4_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C4_DMA
	bool "Enable DMA for I2C4"
	default n
	depends on IMX9_LPI2C_DMA

config IMX9_LPI2C4_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C4_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C4

menuconfig IMX9_LPI2C5
	bool "LPI2C5"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C5

config IMX9_LPI2C5_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C5_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C5_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C5

menuconfig IMX9_LPI2C6
	bool "LPI2C6"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C6

config IMX9_LPI2C6_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C6_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C6_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C6

menuconfig IMX9_LPI2C7
	bool "LPI2C7"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C7

config IMX9_LPI2C7_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C7_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C7_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C7

menuconfig IMX9_LPI2C8
	bool "LPI2C8"
	default n
	select IMX9_LPI2C

if IMX9_LPI2C8

config IMX9_LPI2C8_BUSYIDLE
	int "Bus idle timeout period in clock cycles"
	default 0

config IMX9_LPI2C8_FILTSCL
	int "I2C master digital glitch filters for SCL input in clock cycles"
	default 0

config IMX9_LPI2C8_FILTSDA
	int "I2C master digital glitch filters for SDA input in clock cycles"
	default 0

endif # IMX9_LPI2C8

endmenu # LPI2C Peripherals

menu "LPSPI Peripherals"

menuconfig IMX9_LPSPI1
	bool "LPSPI1"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI2
	bool "LPSPI2"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI3
	bool "LPSPI3"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI4
	bool "LPSPI4"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI5
	bool "LPSPI5"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI6
	bool "LPSPI6"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI7
	bool "LPSPI7"
	default n
	select IMX9_LPSPI

menuconfig IMX9_LPSPI8
	bool "LPSPI8"
	default n
	select IMX9_LPSPI

endmenu # LPSPI Peripherals

menu "eDMA Configuration"
	depends on IMX9_EDMA

config IMX9_EDMA_NTCD
	int "Number of transfer descriptors"
	default 0
	---help---
		Number of pre-allocated transfer descriptors.  Needed for scatter-
		gather DMA.  Make to be set to zero to disable in-memory TCDs in
		which case only the TCD channel registers will be used and scatter-
		will not be supported.

config IMX9_EDMA5_CHAN_OFFSET
	int "Offset of 1st EDMA5 channel"
	default 30
	depends on ARCH_CHIP_IMX95_M7
	---help---
		The EDMA5 controller on the i.MX95 can be accessed by multiple cores.
		However, TCD (Transfer Control Descriptor) mappings are not shareable
		between instances. Instead, each instance must specify its usable TCD
		channels using an offset and count to define a dedicated range.

config IMX9_EDMA5_CHAN_COUNT
	int "Number of EDMA5 channels"
	default 34
	depends on ARCH_CHIP_IMX95_M7
	---help---
		The EDMA5 controller on the i.MX95 can be accessed by multiple cores.
		However, TCD (Transfer Control Descriptor) mappings are not shareable
		between instances. Instead, each instance must specify its usable TCD
		channels using an offset and count to define a dedicated range.

config IMX9_EDMA_ELINK
	bool "Channeling Linking"
	default n
	---help---
		This option enables optional minor or major loop channel linking:

		Minor loop channel linking:  As the channel completes the minor
		loop, this flag enables linking to another channel. The link target
		channel initiates a channel service request via an internal
		mechanism that sets the TCDn_CSR[START] bit of the specified
		channel.

		If minor loop channel linking is disabled, this link mechanism is
		suppressed in favor of the major loop channel linking.

		Major loop channel linking:  As the channel completes the minor
		loop, this option enables the linking to another channel. The link
		target channel initiates a channel service request via an internal
		mechanism that sets the TCDn_CSR[START] bit of the linked channel.

config IMX9_EDMA_ERCA
	bool "Round Robin Channel Arbitration"
	default n
	---help---
		Normally, a fixed priority arbitration is used for channel
		selection.  If this option is selected, round robin arbitration is
		used for channel selection.

config IMX9_EDMA_HOE
	bool "Halt On Error"
	default y
	---help---
		Any error causes the HALT bit to set. Subsequently, all service
		requests are ignored until the HALT bit is cleared.

config IMX9_EDMA_CLM
	bool "Continuous Link Mode"
	default n
	---help---
		By default, A minor loop channel link made to itself goes through
		channel arbitration before being activated again.  If this option is
		selected, a minor loop channel link made to itself does not go
		through channel arbitration before being activated again. Upon minor
		loop completion, the channel activates again if that channel has a
		minor loop channel link enabled and the link channel is itself. This
		effectively applies the minor loop offsets and restarts the next
		minor loop.

config IMX9_EDMA_EMLIM
	bool "Minor Loop Mapping"
	default n
	---help---
		Normally TCD word 2 is a 32-bit NBYTES field.  When this option is
		enabled, TCD word 2 is redefined to include individual enable fields,
		an offset field, and the NBYTES field.  The individual enable fields
		allow the minor loop offset to be applied to the source address, the
		destination address, or both. The NBYTES field is reduced when either
		offset is enabled.

config IMX9_EDMA_EDBG
	bool "Enable Debug"
	default n
	---help---
		When in debug mode, the DMA stalls the start of a new channel. Executing
		channels are allowed to complete. Channel execution resumes when the
		system exits debug mode or the EDBG bit is cleared

endmenu # eDMA Global Configuration

menu "i.MX 95 Memory Configuration"

config IMX9_OCRAM_HEAP
	bool "Add OCRAM to heap"
	depends on !IMX9_OCRAM_PRIMARY
	---help---
		Select to add the entire OCRAM to the heap

config IMX9_INIT_ISRAM
	bool "Calls out to the board code to set instruction RAM"
	---help---
		Some configuration will need to map instruction ram (ITCM)
		this must be done prior to data/bss etc init.

endmenu # i.MX 95 Heap Configuration

menu "LPI2C Configuration"
	depends on IMX9_LPI2C

config IMX9_LPI2C_DMA
	bool "I2C DMA Support"
	default n
	depends on IMX9_LPI2C && IMX9_EDMA && !I2C_POLLED
	---help---
		This option enables the DMA for I2C transfers.
		Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value
		for the I2C dma streams, else the default priority level is set to
		medium.

config IMX9_LPI2C_DMA_MAXMSG
	int "Maximum number messages that will be DMAed"
	default 8
	depends on IMX9_LPI2C_DMA
	---help---
		This option set the number of mesg that can be in a transfer.
		It is used to allocate space for the 16 bit LPI2C commands
		that will be DMA-ed to the LPI2C device.

config IMX9_LPI2C_DYNTIMEO
	bool "Use dynamic timeouts"
	default n
	depends on IMX9_LPI2C

config IMX9_LPI2C_DYNTIMEO_USECPERBYTE
	int "Timeout Microseconds per Byte"
	default 500
	depends on IMX9_LPI2C_DYNTIMEO

config IMX9_LPI2C_DYNTIMEO_STARTSTOP
	int "Timeout for Start/Stop (Milliseconds)"
	default 1000
	depends on IMX9_LPI2C_DYNTIMEO

config IMX9_LPI2C_TIMEOSEC
	int "Timeout seconds"
	default 0
	depends on IMX9_LPI2C

config IMX9_LPI2C_TIMEOMS
	int "Timeout Milliseconds"
	default 500
	depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO

config IMX9_LPI2C_TIMEOTICKS
	int "Timeout for Done and Stop (ticks)"
	default 500
	depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO

endmenu # LPI2C Configuration

menu "LPSPI Configuration"
	depends on IMX9_LPSPI

config IMX9_LPSPI_DMA
	bool "LPSPI DMA"
	depends on IMX9_EDMA
	default n
	---help---
		Use DMA to improve LPSPI transfer performance.

config IMX9_LPSPI_DMATHRESHOLD
	int "LPSPI DMA threshold"
	default 4
	depends on IMX9_LPSPI_DMA
	---help---
		When SPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  But we need a threshold value to determine what
		is small.

config IMX9_LPSPI_HWPCS
	bool "Use native hardware peripheral chip selects instead of GPIO pins"
	default n

config IMX9_LPSPI1_DMA
	bool "LPSPI1 DMA"
	default n
	depends on IMX9_LPSPI1 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve LPSPI1 transfer performance.

config IMX9_LPSPI2_DMA
	bool "LPSPI2 DMA"
	default n
	depends on IMX9_LPSPI2 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve LPSPI2 transfer performance.

config IMX9_LPSPI3_DMA
	bool "LPSPI3 DMA"
	default n
	depends on IMX9_LPSPI3 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve LPSPI3 transfer performance.

config IMX9_LPSPI4_DMA
	bool "LPSPI4 DMA"
	default n
	depends on IMX9_LPSPI4 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve SPI4 transfer performance.

config IMX9_LPSPI5_DMA
	bool "LPSPI5 DMA"
	default n
	depends on IMX9_LPSPI5 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve SPI5 transfer performance.

config IMX9_LPSPI6_DMA
	bool "LPSPI6 DMA"
	default n
	depends on IMX9_LPSPI6 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve SPI6 transfer performance.

config IMX9_LPSPI7_DMA
	bool "LPSPI7 DMA"
	default n
	depends on IMX9_LPSPI7 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve SPI7 transfer performance.

config IMX9_LPSPI8_DMA
	bool "LPSPI8 DMA"
	default n
	depends on IMX9_LPSPI8 && IMX9_LPSPI_DMA
	---help---
		Use DMA to improve SPI8 transfer performance.

endmenu # LPSPI Configuration

menuconfig IMX9_MU
	bool "Mailbox support"
	default y
	depends on IMX9_HAVE_MU

if IMX9_MU

config IMX9_MU5
	bool "MU5 M7 <-> M33"
	default y
	---help---
		Enable mailbox 5 that operates between M7 and M33 cores

config IMX9_MU7
	bool "MU7 M7 <-> A55"
	default n
	---help---
		Enable mailbox 7 that operates between M7 and A55 cores

config IMX9_MU8
	bool "MU8 M7 <-> A55"
	default n
	---help---
		Enable mailbox 5 that operates between M7 and A55 cores

endif # IMX9_MU Configuration

endmenu # iMX Peripheral Selection

endif # ARCH_CHIP_IMX9

